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BCU
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提交内存分配

This commit is contained in:
ahu_gq 2025-06-09 17:59:28 +08:00
parent ccd6ea6432
commit 6985aded2e
7 changed files with 40 additions and 32 deletions
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1
app/stm32fxxx_app/.gitignore vendored
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@ -17,7 +17,6 @@
Objects/
Listings/
Exe/
prj/
# 忽略用户设置文件，通常包含调试和布局等信息
*.uvoptx

2
app/stm32fxxx_app/app/adc_manager.c
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@ -12,7 +12,7 @@
#define MCU_MAX_AD_VALUE 4095
#define ADC_SAMPLE_CNT 250
uint16_t adc_dma_buf[kAdcDataEnd * ADC_SAMPLE_CNT];
uint16_t adc_dma_buf[kAdcDataEnd * ADC_SAMPLE_CNT] __attribute__((section(".ccmram")));
uint32_t adc_value[kAdcDataEnd];
const AdcArray adc_array[kAdcDataEnd] =
{

2
app/stm32fxxx_app/app/bmu_adbms1818.c
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@ -7,7 +7,7 @@
******************************************************************************/
#include "bmu_adbms1818.h"
BmuItem bmu_data;
__attribute__((section(".ccmram"))) BmuItem bmu_data;
static uint8_t adapt_falg = 0;
//adapt ic number

35
app/stm32fxxx_app/prj/BCU_APP.uvprojx
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@ -10,14 +10,14 @@
<TargetName>stm32f407</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC>5050106::V5.05 update 1 (build 106)::ARMCC</pArmCC>
<pCCUsed>5050106::V5.05 update 1 (build 106)::ARMCC</pCCUsed>
<pArmCC>5060750::V5.06 update 6 (build 750)::ARMCC</pArmCC>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32F407ZGTx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F4xx_DFP.2.16.0</PackID>
<PackID>Keil.STM32F4xx_DFP.2.14.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -186,8 +186,6 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -213,7 +211,7 @@
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
@ -354,7 +352,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -363,7 +361,7 @@
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
@ -372,7 +370,7 @@
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\BCU_APP.sct</ScatterFile>
<ScatterFile>.\stm32f407_app.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
@ -473,7 +471,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<ClangAsOpt>0</ClangAsOpt>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -984,7 +982,7 @@
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<ClangAsOpt>0</ClangAsOpt>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -1170,7 +1168,7 @@
<TargetCommonOption>
<Device>STM32F407VGTx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F4xx_DFP.2.16.0</PackID>
<PackID>Keil.STM32F4xx_DFP.2.14.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -1339,8 +1337,6 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -1507,7 +1503,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -2087,13 +2083,4 @@
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>BCU_APP</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

22
app/stm32fxxx_app/prj/stm32f407_app.sct Normal file
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@ -0,0 +1,22 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08020000 0x00100000 { ; load region size_region
ER_IROM1 0x08020000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x0001C000 { ; 112KB SRAM1
.ANY (+RW +ZI)
}
RW_SRAM2 0x2001C000 0x00004000 { ; 16KB SRAM2
*(.sram2)
}
RW_SRAM3 0x10000000 0x00010000 { ; 64KB CCM RAM
*(.ccmram)
}
}

4
library/core/startup_stm32f40xx.s
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@ -39,7 +39,7 @@
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000500
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
@ -50,7 +50,7 @@ __initial_sp
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00003000
Heap_Size EQU 0x00002000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base

6
library/drv_peripheral/drv_qfc41d.c
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@ -9,8 +9,8 @@
#include "drv_qfc41d.h"
#include "eeprom_manager.h"
uint8_t rev_buff[QFC41D_MAX_RECV_SIZE] = {0};
uint8_t send_buff[QFC41D_MAX_SEND_SIZE] = {0};
uint8_t rev_buff[QFC41D_MAX_RECV_SIZE] __attribute__((section(".ccmram")));
uint8_t send_buff[QFC41D_MAX_SEND_SIZE]__attribute__((section(".ccmram")));
#define MAX_PAYLOAD_LEN 128
char cmd[1000] = {0}; //降低栈空间使用
@ -18,7 +18,7 @@ char cmd[1000] = {0}; //
#define TX_DMA_BUFFER_SIZE 2000
volatile uint8_t dma_tx_busy = 0;
uint8_t dma_tx_buffer[2][TX_DMA_BUFFER_SIZE];
uint8_t dma_tx_buffer[2][TX_DMA_BUFFER_SIZE] __attribute__((section(".sram2")));
volatile uint8_t current_buffer = 0; // 0表示正常缓冲区，1表示高优先级缓冲区
//定义