From 6985aded2e6df623703d0146aeba8f04e9033508 Mon Sep 17 00:00:00 2001
From: ahu_gq <57164135+gq-hefei@users.noreply.github.com>
Date: Mon, 9 Jun 2025 17:59:28 +0800
Subject: [PATCH] =?UTF-8?q?=E6=8F=90=E4=BA=A4=E5=86=85=E5=AD=98=E5=88=86?=
=?UTF-8?q?=E9=85=8D?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
app/stm32fxxx_app/.gitignore | 1 -
app/stm32fxxx_app/app/adc_manager.c | 2 +-
app/stm32fxxx_app/app/bmu_adbms1818.c | 2 +-
app/stm32fxxx_app/prj/BCU_APP.uvprojx | 35 ++++++++-----------------
app/stm32fxxx_app/prj/stm32f407_app.sct | 22 ++++++++++++++++
library/core/startup_stm32f40xx.s | 4 +--
library/drv_peripheral/drv_qfc41d.c | 6 ++---
7 files changed, 40 insertions(+), 32 deletions(-)
create mode 100644 app/stm32fxxx_app/prj/stm32f407_app.sct
diff --git a/app/stm32fxxx_app/.gitignore b/app/stm32fxxx_app/.gitignore
index 437af95..e71aa2d 100644
--- a/app/stm32fxxx_app/.gitignore
+++ b/app/stm32fxxx_app/.gitignore
@@ -17,7 +17,6 @@
Objects/
Listings/
Exe/
-prj/
# 忽略用户设置文件，通常包含调试和布局等信息
*.uvoptx
diff --git a/app/stm32fxxx_app/app/adc_manager.c b/app/stm32fxxx_app/app/adc_manager.c
index 722e1b9..23a2388 100644
--- a/app/stm32fxxx_app/app/adc_manager.c
+++ b/app/stm32fxxx_app/app/adc_manager.c
@@ -12,7 +12,7 @@
#define MCU_MAX_AD_VALUE 4095
#define ADC_SAMPLE_CNT 250
-uint16_t adc_dma_buf[kAdcDataEnd * ADC_SAMPLE_CNT];
+uint16_t adc_dma_buf[kAdcDataEnd * ADC_SAMPLE_CNT] __attribute__((section(".ccmram")));
uint32_t adc_value[kAdcDataEnd];
const AdcArray adc_array[kAdcDataEnd] =
{
diff --git a/app/stm32fxxx_app/app/bmu_adbms1818.c b/app/stm32fxxx_app/app/bmu_adbms1818.c
index f3f1820..9c9ccc3 100644
--- a/app/stm32fxxx_app/app/bmu_adbms1818.c
+++ b/app/stm32fxxx_app/app/bmu_adbms1818.c
@@ -7,7 +7,7 @@
******************************************************************************/
#include "bmu_adbms1818.h"
-BmuItem bmu_data;
+__attribute__((section(".ccmram"))) BmuItem bmu_data;
static uint8_t adapt_falg = 0;
//adapt ic number
diff --git a/app/stm32fxxx_app/prj/BCU_APP.uvprojx b/app/stm32fxxx_app/prj/BCU_APP.uvprojx
index 5afa791..fa7cb56 100644
--- a/app/stm32fxxx_app/prj/BCU_APP.uvprojx
+++ b/app/stm32fxxx_app/prj/BCU_APP.uvprojx
@@ -10,14 +10,14 @@
stm32f407
0x4
ARM-ADS
- 5050106::V5.05 update 1 (build 106)::ARMCC
- 5050106::V5.05 update 1 (build 106)::ARMCC
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 5060750::V5.06 update 6 (build 750)::ARMCC
0
STM32F407ZGTx
STMicroelectronics
- Keil.STM32F4xx_DFP.2.16.0
+ Keil.STM32F4xx_DFP.2.14.0
http://www.keil.com/pack/
IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
@@ -186,8 +186,6 @@
0
2
0
- 0
- 0
1
0
8
@@ -213,7 +211,7 @@
0
0
1
- 0
+ 1
0
@@ -354,7 +352,7 @@
0
0
0
- 4
+ 0
@@ -363,7 +361,7 @@
- 1
+ 0
0
0
0
@@ -372,7 +370,7 @@
0x08000000
0x20000000
- .\BCU_APP.sct
+ .\stm32f407_app.sct
@@ -473,7 +471,7 @@
2
2
2
- 0
+ 2
@@ -984,7 +982,7 @@
2
2
2
- 0
+ 2
@@ -1170,7 +1168,7 @@
STM32F407VGTx
STMicroelectronics
- Keil.STM32F4xx_DFP.2.16.0
+ Keil.STM32F4xx_DFP.2.14.0
http://www.keil.com/pack/
IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
@@ -1339,8 +1337,6 @@
0
2
0
- 0
- 0
1
0
8
@@ -1507,7 +1503,7 @@
0
0
0
- 4
+ 0
@@ -2087,13 +2083,4 @@
-
-
-
- BCU_APP
- 1
-
-
-
-
diff --git a/app/stm32fxxx_app/prj/stm32f407_app.sct b/app/stm32fxxx_app/prj/stm32f407_app.sct
new file mode 100644
index 0000000..4fa4f17
--- /dev/null
+++ b/app/stm32fxxx_app/prj/stm32f407_app.sct
@@ -0,0 +1,22 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08020000 0x00100000 { ; load region size_region
+ ER_IROM1 0x08020000 0x00100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x0001C000 { ; 112KB SRAM1
+ .ANY (+RW +ZI)
+ }
+ RW_SRAM2 0x2001C000 0x00004000 { ; 16KB SRAM2
+ *(.sram2)
+ }
+ RW_SRAM3 0x10000000 0x00010000 { ; 64KB CCM RAM
+ *(.ccmram)
+ }
+}
+
diff --git a/library/core/startup_stm32f40xx.s b/library/core/startup_stm32f40xx.s
index 50b97f1..144a7d6 100644
--- a/library/core/startup_stm32f40xx.s
+++ b/library/core/startup_stm32f40xx.s
@@ -39,7 +39,7 @@
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
-Stack_Size EQU 0x00000500
+Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
@@ -50,7 +50,7 @@ __initial_sp
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
-Heap_Size EQU 0x00003000
+Heap_Size EQU 0x00002000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
diff --git a/library/drv_peripheral/drv_qfc41d.c b/library/drv_peripheral/drv_qfc41d.c
index 872934e..3a9d8d5 100644
--- a/library/drv_peripheral/drv_qfc41d.c
+++ b/library/drv_peripheral/drv_qfc41d.c
@@ -9,8 +9,8 @@
#include "drv_qfc41d.h"
#include "eeprom_manager.h"
-uint8_t rev_buff[QFC41D_MAX_RECV_SIZE] = {0};
-uint8_t send_buff[QFC41D_MAX_SEND_SIZE] = {0};
+uint8_t rev_buff[QFC41D_MAX_RECV_SIZE] __attribute__((section(".ccmram")));
+uint8_t send_buff[QFC41D_MAX_SEND_SIZE]__attribute__((section(".ccmram")));
#define MAX_PAYLOAD_LEN 128
char cmd[1000] = {0}; //ջռʹ
@@ -18,7 +18,7 @@ char cmd[1000] = {0}; //
#define TX_DMA_BUFFER_SIZE 2000
volatile uint8_t dma_tx_busy = 0;
-uint8_t dma_tx_buffer[2][TX_DMA_BUFFER_SIZE];
+uint8_t dma_tx_buffer[2][TX_DMA_BUFFER_SIZE] __attribute__((section(".sram2")));
volatile uint8_t current_buffer = 0; // 0ʾ1ʾȼ
//