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No commits in common. "83b4133c689d9656967ca7d80361acaa4d0318b4" and "c2cceee9df17603d63e02005683009d3bd171320" have entirely different histories.
83b4133c68
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c2cceee9df
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@ -5,8 +5,6 @@
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*.rpt
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*.rpt
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*.plg
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*.plg
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*.uvgui.*
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*.uvgui.*
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*.uvprojx
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*.uv*
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*.crf
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*.crf
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*.map
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*.map
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*.hex
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*.hex
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@ -17,8 +17,8 @@
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<TargetCommonOption>
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<TargetCommonOption>
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<Device>STM32F407ZGTx</Device>
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<Device>STM32F407ZGTx</Device>
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<Vendor>STMicroelectronics</Vendor>
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<Vendor>STMicroelectronics</Vendor>
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<PackID>Keil.STM32F4xx_DFP.2.14.0</PackID>
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<PackID>Keil.STM32F4xx_DFP.3.0.0</PackID>
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<PackURL>http://www.keil.com/pack/</PackURL>
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<PackURL>https://www.keil.com/pack/</PackURL>
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<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
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<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
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<FlashUtilSpec></FlashUtilSpec>
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<FlashUtilSpec></FlashUtilSpec>
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<StartupFile></StartupFile>
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<StartupFile></StartupFile>
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@ -186,6 +186,8 @@
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<uocXRam>0</uocXRam>
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<uocXRam>0</uocXRam>
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<RvdsVP>2</RvdsVP>
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<RvdsVP>2</RvdsVP>
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<RvdsMve>0</RvdsMve>
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<RvdsMve>0</RvdsMve>
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<RvdsCdeCp>0</RvdsCdeCp>
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<nBranchProt>0</nBranchProt>
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<hadIRAM2>1</hadIRAM2>
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<hadIRAM2>1</hadIRAM2>
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<hadIROM2>0</hadIROM2>
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<hadIROM2>0</hadIROM2>
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<StupSel>8</StupSel>
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<StupSel>8</StupSel>
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@ -352,7 +354,7 @@
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<NoWarn>0</NoWarn>
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<NoWarn>0</NoWarn>
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<uSurpInc>0</uSurpInc>
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<uSurpInc>0</uSurpInc>
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<useXO>0</useXO>
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<useXO>0</useXO>
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<uClangAs>0</uClangAs>
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<ClangAsOpt>4</ClangAsOpt>
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<VariousControls>
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<VariousControls>
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<MiscControls></MiscControls>
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<MiscControls></MiscControls>
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<Define></Define>
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<Define></Define>
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@ -471,7 +473,7 @@
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<NoWarn>2</NoWarn>
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<NoWarn>2</NoWarn>
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<uSurpInc>2</uSurpInc>
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<uSurpInc>2</uSurpInc>
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<useXO>2</useXO>
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<useXO>2</useXO>
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<uClangAs>2</uClangAs>
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<ClangAsOpt>0</ClangAsOpt>
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<VariousControls>
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<VariousControls>
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<MiscControls></MiscControls>
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<MiscControls></MiscControls>
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<Define></Define>
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<Define></Define>
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@ -972,7 +974,7 @@
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<NoWarn>2</NoWarn>
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<NoWarn>2</NoWarn>
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<uSurpInc>2</uSurpInc>
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<uSurpInc>2</uSurpInc>
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<useXO>2</useXO>
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<useXO>2</useXO>
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<uClangAs>2</uClangAs>
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<ClangAsOpt>0</ClangAsOpt>
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<VariousControls>
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<VariousControls>
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<MiscControls></MiscControls>
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<MiscControls></MiscControls>
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<Define></Define>
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<Define></Define>
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@ -1312,6 +1314,8 @@
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<uocXRam>0</uocXRam>
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<uocXRam>0</uocXRam>
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<RvdsVP>2</RvdsVP>
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<RvdsVP>2</RvdsVP>
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<RvdsMve>0</RvdsMve>
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<RvdsMve>0</RvdsMve>
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<RvdsCdeCp>0</RvdsCdeCp>
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<nBranchProt>0</nBranchProt>
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<hadIRAM2>1</hadIRAM2>
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<hadIRAM2>1</hadIRAM2>
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<hadIROM2>0</hadIROM2>
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<hadIROM2>0</hadIROM2>
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<StupSel>8</StupSel>
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<StupSel>8</StupSel>
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@ -1478,7 +1482,7 @@
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<NoWarn>0</NoWarn>
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<NoWarn>0</NoWarn>
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<uSurpInc>0</uSurpInc>
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<uSurpInc>0</uSurpInc>
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<useXO>0</useXO>
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<useXO>0</useXO>
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<uClangAs>0</uClangAs>
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<ClangAsOpt>4</ClangAsOpt>
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<VariousControls>
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<VariousControls>
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<MiscControls></MiscControls>
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<MiscControls></MiscControls>
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<Define></Define>
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<Define></Define>
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