313 lines
8.5 KiB
C
313 lines
8.5 KiB
C
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#include "drv_dma.h"
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#include "drv_clk.h"
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#include "drv_misc.h"
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#include "kit_time.h"
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#include "kit_debug.h"
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#define DMA_IT_TC ((uint32_t)0x00000002)
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#define DMA_IT_HT ((uint32_t)0x00000004)
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#define DMA_IT_TE ((uint32_t)0x00000008)
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#define DMA_CCR_EN ((uint32_t)0x00000001)
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#define DMA1_IT_TE2 ((uint32_t)0x00000080)
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#define DMA1_IT_TC2 ((uint32_t)0x00000020)
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#define DMA_Mode_Normal ((uint32_t)0x00000000)
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#define DMA_Mode_Circular ((uint32_t)0x00000020)
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#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
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#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
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#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
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#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
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#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
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#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
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#define DMA_STREAM3_IT_ERR ((uint32_t)0x03400000)
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#define DMA_STREAM3_IT_FLAG ((uint32_t)0x0F400000)
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typedef enum
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{
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kDmaIdx_0,
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kDmaIdx_1,
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kDmaIdx_End,
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}DmaIdx;
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typedef struct
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{
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uint8_t irq;
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uint8_t ch_id; //通道实际编号,如通道5编号为4
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DmaIdx dma_idx;
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DMA_Stream_TypeDef *channel_reg;
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}Stm32DmaProp;
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static KitIrqCall dma_irq_call[kDmaStream_End];
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const DMA_TypeDef * dma_array[kDmaIdx_End] = {DMA1, DMA2};
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static const Stm32DmaProp stm32_dma[kDmaStream_End] =
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{
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{DMA1_Stream0_IRQn, 0, kDmaIdx_0, DMA1_Stream0},
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{DMA1_Stream1_IRQn, 1, kDmaIdx_0, DMA1_Stream1},
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{DMA1_Stream2_IRQn, 2, kDmaIdx_0, DMA1_Stream2},
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{DMA1_Stream3_IRQn, 3, kDmaIdx_0, DMA1_Stream3},
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{DMA1_Stream4_IRQn, 4, kDmaIdx_0, DMA1_Stream4},
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{DMA1_Stream5_IRQn, 5, kDmaIdx_0, DMA1_Stream5},
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{DMA1_Stream6_IRQn, 6, kDmaIdx_0, DMA1_Stream6},
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{DMA1_Stream7_IRQn, 7, kDmaIdx_0, DMA1_Stream7},
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{DMA2_Stream0_IRQn, 0, kDmaIdx_1, DMA2_Stream0},
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{DMA2_Stream1_IRQn, 1, kDmaIdx_1, DMA2_Stream1},
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{DMA2_Stream2_IRQn, 2, kDmaIdx_1, DMA2_Stream2},
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{DMA2_Stream3_IRQn, 3, kDmaIdx_1, DMA2_Stream3},
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{DMA2_Stream4_IRQn, 4, kDmaIdx_1, DMA2_Stream4},
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{DMA2_Stream5_IRQn, 5, kDmaIdx_1, DMA2_Stream5},
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{DMA2_Stream6_IRQn, 6, kDmaIdx_1, DMA2_Stream6},
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{DMA2_Stream7_IRQn, 6, kDmaIdx_1, DMA2_Stream7},
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};
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#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
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void dma_reset(DmaStream stream_idx)
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{
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DMA_Stream_TypeDef* DMAy_Streamx = stm32_dma[stream_idx].channel_reg;
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DMAy_Streamx->CR &= (uint16_t)(~DMA_SxCR_EN);
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/* Reset DMAy Channelx control register */
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DMAy_Streamx->CR = 0;
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/* Reset DMAy Channelx remaining bytes register */
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DMAy_Streamx->NDTR = 0;
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/* Reset DMAy Channelx peripheral address register */
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DMAy_Streamx->PAR = 0;
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/* Reset DMAy Channelx memory address register */
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DMAy_Streamx->M0AR = 0;
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DMAy_Streamx->M1AR = 0;
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DMAy_Streamx->FCR = (uint32_t)0x00000021;
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}
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const uint32_t dma_clk_en[kDmaIdx_End] = {RCC_AHB1ENR_DMA1EN, RCC_AHB1ENR_DMA2EN};
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KitResult drv_dma_init(DmaStream stream_idx, DmaChannel channel, uint32_t dma_config, uint32_t addr)
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{
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uint32_t reg = 0;
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KitResult res = kKitResult_Ok;
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KIT_ASSERT_PARAM((stream_idx < kDmaStream_End) && (addr != NULL));
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if((stream_idx < kDmaStream_End) && (addr != NULL))
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{
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RCC->AHB1ENR |= dma_clk_en[stm32_dma[stream_idx].dma_idx]; //开启时钟
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//dma初始化
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dma_reset(stream_idx);
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if((dma_config & DMA_CFG_DATA_DIR_M2P) == DMA_CFG_DATA_DIR_M2P)
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{
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reg |= KIT_CREAT_BIT(6);
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}
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else if((dma_config & DMA_CFG_DATA_DIR_M2M) == DMA_CFG_DATA_DIR_M2P)
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{
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reg |= KIT_CREAT_BIT(7);
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}
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if((dma_config & DMA_CFG_CYCLE_EXE) == DMA_CFG_CYCLE_EXE)
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{
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reg |= KIT_CREAT_BIT(8);
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}
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if((dma_config & DMA_CFG_DATA_P_I) == DMA_CFG_DATA_P_I)
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{
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reg |= KIT_CREAT_BIT(9);
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}
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if((dma_config & DMA_CFG_DATA_M_I) == DMA_CFG_DATA_M_I)
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{
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reg |= KIT_CREAT_BIT(10);
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}
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if((dma_config & DMA_CFG_DATA_LEN_2B) == DMA_CFG_DATA_LEN_2B)
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{
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reg |= (KIT_CREAT_BIT(11) | KIT_CREAT_BIT(13));
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}
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else if((dma_config & DMA_CFG_DATA_LEN_4B) == DMA_CFG_DATA_LEN_4B)
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{
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reg |= (KIT_CREAT_BIT(12) | KIT_CREAT_BIT(14));
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}
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reg |= ((uint32_t)channel) << 25;
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stm32_dma[stream_idx].channel_reg->CR |= reg;
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stm32_dma[stream_idx].channel_reg->PAR = addr;
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}
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else
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{
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res = kKitResult_ParamErr;
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}
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return res;
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}
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void drv_dma_set_interrupt(DmaStream stream_idx, uint8_t priority, KitIrqCall call)
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{
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KIT_ASSERT_PARAM(stream_idx < kDmaStream_End);
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stm32_dma[stream_idx].channel_reg->CR |= (DMA_SxCR_TCIE | DMA_SxCR_TEIE);
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drv_misc_set_nvic(stm32_dma[stream_idx].irq, priority);
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dma_irq_call[stream_idx] = call;
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}
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__IO uint32_t * dma_ifcr[4] = {&DMA1->LIFCR, &DMA1->HIFCR, &DMA2->LIFCR, &DMA2->HIFCR};
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const uint32_t dma_ifcr_clr_bit[4] = {0x0000003D, 0x00000F40, 0x003D0000, 0x0F400000};
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//传输错误或者结束标志位
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__IO uint32_t * dma_isr[4] = {&DMA1->LISR, &DMA1->HISR, &DMA2->LISR, &DMA2->HISR};
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const uint32_t dma_isr_transfer_end_bit[4] = {0x0000002C, 0x00000B00, 0x002C0000, 0x0B000000};
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void drv_dma_set_buf(DmaStream stream_idx,uint8_t* buf, uint16_t len)
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{
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DMA_Stream_TypeDef * stream_reg;
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KIT_ASSERT_PARAM((buf != NULL) && (len > 0));
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KIT_ASSERT_PARAM(stream_idx < kDmaStream_End);
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if((stream_idx < kDmaStream_End) && (buf != NULL))
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{
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stream_reg = stm32_dma[stream_idx].channel_reg;
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//清除标志位
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*dma_ifcr[stream_idx / 4] |= dma_ifcr_clr_bit[stream_idx % 4];
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stream_reg->NDTR = len;
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stream_reg->M0AR = (uint32_t)buf;
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stream_reg->CR |= DMA_CCR_EN;
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}
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}
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KitResult drv_dma_send(DmaStream dma_tx_ch, uint8_t *tx_buf, uint16_t tx_len)
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{
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uint32_t dly = 0;
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KitResult res = kKitResult_Ok;
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KIT_ASSERT_PARAM((tx_buf != NULL) && (tx_len > 0));
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drv_dma_set_buf(dma_tx_ch, tx_buf, tx_len);
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//等待接收完成
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while((*dma_isr[dma_tx_ch >> 2] & dma_isr_transfer_end_bit[dma_tx_ch % 4]) == 0)
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{
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kit_time_dly_ms(1);
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if(++dly > 500)
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{
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res = kKitResult_TimeOut;
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break;
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}
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}
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stm32_dma[dma_tx_ch].channel_reg->CR &= ~DMA_CCR_EN ; //关闭DMA通道2
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return res;
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}
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KitResult drv_dma_receive(DmaStream dma_rx_ch, DmaStream dma_tx_ch, uint8_t *rx_buf, uint16_t rx_len)
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{
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uint32_t dly = 0;
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KitResult res = kKitResult_Ok;
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KIT_ASSERT_PARAM(timeout > 0);
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KIT_ASSERT_PARAM(((tx_buf != NULL) && (tx_len > 0)) || ((tx_buf == NULL) && (tx_len == 0)));
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KIT_ASSERT_PARAM(((rx_buf != NULL) && (rx_len > 0)) || ((rx_buf == NULL) && (rx_len == 0)));
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drv_dma_set_buf(dma_rx_ch, rx_buf, rx_len);
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drv_dma_set_buf(dma_tx_ch, rx_buf, rx_len);
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//等待接收完成
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while((*dma_isr[dma_rx_ch >> 2] & dma_isr_transfer_end_bit[dma_rx_ch % 4]) == 0)
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{
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kit_time_dly_ms(1);
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if(++dly > 200)
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{
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res = kKitResult_TimeOut;
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break;
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}
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}
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stm32_dma[dma_tx_ch].channel_reg->CR &= ~DMA_CCR_EN ; //关闭DMA通道3
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stm32_dma[dma_tx_ch].channel_reg->CR &= ~DMA_CCR_EN ; //关闭DMA通道2
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return res;
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}
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void DMA1_Stream0_IRQHandler(void)
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{
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}
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void DMA1_Stream1_IRQHandler(void)
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{
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}
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void DMA1_Stream2_IRQHandler(void)
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{
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}
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void DMA1_Stream3_IRQHandler(void)
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{
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KitResult res = kKitResult_Ok;
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DMA1_Stream3->CR &= ~DMA_CCR_EN ; //关闭DMA通道2
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DMA1_Stream4->CR &= ~DMA_CCR_EN ; //关闭DMA通道3
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if((DMA1->LISR & DMA_STREAM3_IT_ERR) != 0)
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{
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KIT_ASSERT_RES(0, kKitResult_Error);
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res = kKitResult_Error;
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}
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DMA1->LIFCR = DMA_STREAM3_IT_FLAG; //清楚标志位
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if(dma_irq_call[kDma1Stream_3] != NULL)
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dma_irq_call[kDma1Stream_3](res, NULL);
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}
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void DMA1_Stream4_IRQHandler(void)
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{
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}
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void DMA1_Stream5_IRQHandler(void)
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{
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}
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void DMA1_Channel6_IRQHandler(void)
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{
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}
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void DMA2_Stream0_IRQHandler(void)
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{
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}
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void DMA2_Stream1_IRQHandler(void)
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{
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}
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void DMA2_Stream2_IRQHandler(void)
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{
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}
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void DMA2_Stream3_IRQHandler(void)
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{
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}
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void DMA2_Stream4_IRQHandler(void)
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{
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}
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void DMA2_Stream5_IRQHandler(void)
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{
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}
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void DMA2_Stream6_IRQHandler(void)
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{
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}
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void DMA2_Stream7_IRQHandler(void)
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{
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}
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