162 lines
6.6 KiB
ArmAsm
162 lines
6.6 KiB
ArmAsm
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/*
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*********************************************************************************************************
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* uC/CPU
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* CPU CONFIGURATION & PORT LAYER
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*
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* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* CPU PORT FILE
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*
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* MicroBlaze
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* GNU C Compiler
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*
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* Filename : cpu_a.S
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* Version : V1.32.01
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*********************************************************************************************************
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*/
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#define _ASMLANGUAGE
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#include <cpu_cfg.h>
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/*
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*********************************************************************************************************
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* PUBLIC FUNCTIONS
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*********************************************************************************************************
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*/
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.globl CPU_SR_Save
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.globl CPU_SR_Restore
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/*
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*********************************************************************************************************
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* EQUATES
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*********************************************************************************************************
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*/
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.equ CPU_IE_BIT, 0x02
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.text
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/*
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*********************************************************************************************************
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* DISABLE INTERRUPTS
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* CPU_SR CPU_SR_Save(void);
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*
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* Description : Disables the interrupts and returns the RMSR contents. This allows the IE state to be
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* restored at a subsequent time.
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*
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* The variable in the calling routine which the return is set to MUST be declared 'volatile'
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* for proper operation. There is no guarantee that the proper register will be scheduled
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* for the subsequent 'CPU_SR_Save()' function call if the variable is not declared
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* 'volatile'.
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*
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* Arguments : None
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*
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* Returns : Current RMSR contents in R3
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*
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* Note(s) : This function uses the MSRCLR instruction, which is not, by default, recognized by
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* MicroBlaze processors. Setting the paramter C_USE_MSR_INSTR to '1' in the MHS file
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* allows the processor to recognize this instruction.
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*********************************************************************************************************
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*/
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#ifdef CPU_CFG_MB_HAS_MSR_INST
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CPU_SR_Save:
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RTSD r15, 8
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MSRCLR r3, CPU_IE_BIT /* Save MSR in r3 and disable interrupts */
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#else
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CPU_SR_Save:
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ADDIK r1, r1, -4 /* Save R4 since it's used as a scratchpad register */
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SW r4, r1, r0
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MFS r3, RMSR /* Read the MSR. r3 is used as the return value */
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ANDNI r4, r3, CPU_IE_BIT /* Mask off the IE bit */
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MTS RMSR, r4 /* Store the MSR */
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LW r4, r1, r0 /* Restore R4 */
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ADDIK r1, r1, 4
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AND r0, r0, r0 /* NO-OP - pipeline flush */
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AND r0, r0, r0 /* NO-OP - pipeline flush */
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AND r0, r0, r0 /* NO-OP - pipeline flush */
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RTSD r15, 8 /* Return to caller with R3 containing original RMSR */
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AND r0, r0, r0 /* NO-OP */
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#endif
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/*
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*********************************************************************************************************
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* ENABLE INTERRUPTS
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* void CPU_SR_Restore(CPU_SR sr);
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*
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* Description: Enables the interrupts using the provided data. If the IE bit is set in the argument, the
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* RTID opcode is used to return. If the IE bis is clear, the standard RTSD is used leaving
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* the interrupts disabled.
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*
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* The argument from the calling routine MUST be declared 'volatile' for proper operation.
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* There is no guarantee that the proper register will be scheduled for the 'CPU_SR_Restore()'
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* function call if the variable is not declared 'volatile'.
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*
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* Arguments : Saved RMSR contents in R5
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*
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* Returns : None
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*
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* Note(s) : None
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*********************************************************************************************************
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*/
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CPU_SR_Restore:
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RTSD r15, 8
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MTS rMSR, r5 /* Move the saved status from r5 into rMSR */
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/*
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********************************************************************************************************
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* CPU_CntLeadZeros()
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* COUNT LEADING ZEROS
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*
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* Description : Counts the number of contiguous, most-significant, leading zero bits before the first
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* binary one bit in a data value.
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*
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* Prototype : CPU_DATA CPU_CntLeadZeros(CPU_DATA val);
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*
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* Argument(s) : val Data value to count leading zero bits.
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*
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* Return(s) : Number of contiguous, most-significant, leading zero bits in 'val'.
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*
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* Note(s) : (1) If the argument is zero, the value 32 is returned.
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*
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* (2) MUST be implemented in cpu_a.asm if and only if CPU_CFG_LEAD_ZEROS_ASM_PRESENT is
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* #define'd in 'cpu_cfg.h' or 'cpu.h'.
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********************************************************************************************************
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*/
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#ifdef CPU_CFG_LEAD_ZEROS_ASM_PRESENT
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.globl CPU_CntLeadZeros
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CPU_CntLeadZeros:
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RTSD r15, 8
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CLZ r3, r5
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#endif
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/*
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*********************************************************************************************************
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* CPU ASSEMBLY PORT FILE END
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*********************************************************************************************************
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*/
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