131 lines
5.4 KiB
ArmAsm
131 lines
5.4 KiB
ArmAsm
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/*
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*********************************************************************************************************
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* uC/CPU
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* CPU CONFIGURATION & PORT LAYER
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*
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* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* CPU PORT FILE
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*
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* PPC405
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* GNU C Compiler
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*
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* Filename : cpu_a.s
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* Version : V1.32.01
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*********************************************************************************************************
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*/
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#define _ASMLANGUAGE
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/*
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*********************************************************************************************************
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* PUBLIC FUNCTIONS
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*********************************************************************************************************
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*/
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.globl CPU_SR_Save
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.globl CPU_SR_Restore
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.text
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/*
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*********************************************************************************************************
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* CRITICAL SECTION FUNCTIONS
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*
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* Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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* state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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* are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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* The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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*
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* Prototypes : CPU_SR CPU_SR_Save (void);
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* void CPU_SR_Restore(CPU_SR cpu_sr);
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*
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* Note(s) : (1) These functions are used in general like this :
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*
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* void Task (void *p_arg)
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* {
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* CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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* :
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* :
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* CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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* :
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* :
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* CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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* :
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* }
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* DISABLE INTERRUPTS
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* CPU_SR CPU_SR_Save(void);
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*
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* Description : Sets the MSR, disabling interrupts, and returns the previous MSR contents. This allows
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* the machine state to be restored at a subsequent time.
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*
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* Arguments : None
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*
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* Returns : Current MSR contents in GPR3
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*
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* Note(s) : 1) The variable in the calling routine that will hold the return value MUST be declared
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* volatile for proper operation. There is no guarantee that the proper register will
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* be scheduled for the subsequent 'CPU_SR_Save()' function call if the variable is
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* not declared volatile.
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*********************************************************************************************************
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*/
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CPU_SR_Save:
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addis 4, 0, 0xFFFD
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ori 4, 4, 0x7FFF
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mfmsr 3
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and 4, 4, 3 /* Clear bits 14 and 16, corresponding to... */
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mtmsr 4 /* ...critical and non-critical interrupts */
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blr
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/*
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*********************************************************************************************************
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* ENABLE INTERRUPTS
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* void CPU_SR_Restore(CPU_SR sr);
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*
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* Description : Sets the MSR, possibly enabling interrupts, using the value passed in GPR3.
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*
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* Arguments : Saved MSR contents in GPR3
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*
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* Returns : None
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*
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* Note(s) : 1) The argument from the calling routine MUST be declared volatile for proper operation.
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* There is no guarantee that the proper register will be scheduled for the call to
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* CPU_SR_Restore() if the variable is not declared 'volatile'.
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*********************************************************************************************************
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*/
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CPU_SR_Restore:
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mtmsr 3 /* Restore the saved MSR */
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blr
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/*
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*********************************************************************************************************
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* CPU ASSEMBLY PORT FILE END
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*********************************************************************************************************
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*/
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