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bs_bcu_app/tmp/sys.c

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2024-11-07 17:24:19 +08:00
/**
****************************************************************************************************
* @file sys.c
* @author <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><EFBFBD><EFBFBD>Ŷ<EFBFBD>(ALIENTEK)
* @version V1.0
* @date 2021-10-14
* @brief ϵͳ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<EFBFBD>жϹ<EFBFBD><EFBFBD><EFBFBD>/GPIO<EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>)
* @license Copyright (c) 2020-2032, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>޹<EFBFBD>˾
****************************************************************************************************
* @attention
*
* ʵ<EFBFBD><EFBFBD>ƽ̨:<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><EFBFBD> ̽<EFBFBD><EFBFBD><EFBFBD><EFBFBD> F407<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ:www.yuanzige.com
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
* <EFBFBD><EFBFBD>˾<EFBFBD><EFBFBD>ַ:www.alientek.com
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ:openedv.taobao.com
*
* <EFBFBD>޸<EFBFBD>˵<EFBFBD><EFBFBD>
* V1.0 20211014
* <EFBFBD><EFBFBD>һ<EFBFBD>η<EFBFBD><EFBFBD><EFBFBD>
****************************************************************************************************
*/
#include "./SYSTEM/sys/sys.h"
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
* @param baseaddr: <EFBFBD><EFBFBD>ַ
* @param offset: ƫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_nvic_set_vector_table(uint32_t baseaddr, uint32_t offset)
{
/* <20><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>,VTOR<4F><52>9λ<39><CEBB><EFBFBD><EFBFBD>,<2C><>[8:0]<5D><><EFBFBD><EFBFBD> */
SCB->VTOR = baseaddr | (offset & (uint32_t)0xFFFFFE00);
}
/**
* @brief ִ<EFBFBD><EFBFBD>: WFIָ<EFBFBD><EFBFBD>(ִ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͹<EFBFBD><EFBFBD><EFBFBD>״̬, <EFBFBD>ȴ<EFBFBD><EFBFBD>жϻ<EFBFBD><EFBFBD><EFBFBD>)
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_wfi_set(void)
{
__ASM volatile("wfi");
}
/**
* @brief <EFBFBD>ر<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<EFBFBD><EFBFBD><EFBFBD>Dz<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>fault<EFBFBD><EFBFBD>NMI<EFBFBD>ж<EFBFBD>)
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_intx_disable(void)
{
__ASM volatile("cpsid i");
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_intx_enable(void)
{
__ASM volatile("cpsie i");
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֺ<EFBFBD>X, <EFBFBD><EFBFBD><EFBFBD><EFBFBD>MDK<EFBFBD><EFBFBD><EFBFBD><EFBFBD>, ʵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param addr: ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
* @retval <EFBFBD><EFBFBD>
*/
void sys_msr_msp(uint32_t addr)
{
__set_MSP(addr); /* <20><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ */
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_standby(void)
{
__HAL_RCC_PWR_CLK_ENABLE(); /* ʹ<>ܵ<EFBFBD>Դʱ<D4B4><CAB1> */
SET_BIT(PWR->CR, PWR_CR_PDDS); /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ */
}
/**
* @brief ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
* @param <EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void sys_soft_reset(void)
{
NVIC_SystemReset();
}
/**
* @brief ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>
* @param plln: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL<EFBFBD><EFBFBD>Ƶ), ȡֵ<EFBFBD><EFBFBD>Χ: 64~432.
* @param pllm: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƵPLLԤ<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(<EFBFBD><EFBFBD>PLL֮ǰ<EFBFBD>ķ<EFBFBD>Ƶ), ȡֵ<EFBFBD><EFBFBD>Χ: 2~63.
* @param pllp: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>p<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ), <EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊϵͳʱ<EFBFBD><EFBFBD>, ȡֵ<EFBFBD><EFBFBD>Χ: 2, 4, 6, 8.(<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>ֵ)
* @param pllq: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>q<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ), ȡֵ<EFBFBD><EFBFBD>Χ: 2~15.
* @note
*
* Fvco: VCOƵ<EFBFBD><EFBFBD>
* Fsys: ϵͳʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>, Ҳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>p<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>
* Fq: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>q<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>
* Fs: <EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HSI, HSE<EFBFBD><EFBFBD>.
* Fvco = Fs * (plln / pllm);
* Fsys = Fvco / pllp = Fs * (plln / (pllm * pllp));
* Fq = Fvco / pllq = Fs * (plln / (pllm * pllq));
*
* <EFBFBD>ⲿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ 8M<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>, <EFBFBD>Ƽ<EFBFBD>ֵ: plln = 336, pllm = 8, pllp = 2, pllq = 7.
* <EFBFBD>õ<EFBFBD>:Fvco = 8 * (336 / 8) = 336Mhz
* Fsys = pll_p_ck = 336 / 2 = 168Mhz
* Fq = pll_q_ck = 336 / 7 = 48Mhz
*
* F407Ĭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
* CPUƵ<EFBFBD><EFBFBD>(HCLK) = pll_p_ck = 168Mhz
* AHB1/2/3(rcc_hclk1/2/3) = 168Mhz
* APB1(rcc_pclk1) = pll_p_ck / 4 = 42Mhz
* APB1(rcc_pclk2) = pll_p_ck / 2 = 84Mhz
*
* @retval <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0, <EFBFBD>ɹ<EFBFBD>; 1, <EFBFBD><EFBFBD><EFBFBD><EFBFBD>;
*/
uint8_t sys_stm32_clock_init(uint32_t plln, uint32_t pllm, uint32_t pllp, uint32_t pllq)
{
HAL_StatusTypeDef ret = HAL_OK;
RCC_OscInitTypeDef rcc_osc_init = {0};
RCC_ClkInitTypeDef rcc_clk_init = {0};
__HAL_RCC_PWR_CLK_ENABLE(); /* ʹ<><CAB9>PWRʱ<52><CAB1> */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* <20><><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD> */
/* ʹ<><CAB9>HSE<53><45><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>HSE<53><45>ΪPLLʱ<4C><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL1<4C><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>USBʱ<42><CAB1> */
rcc_osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE; /* ʱ<><CAB1>ԴΪHSE */
rcc_osc_init.HSEState = RCC_HSE_ON; /* <20><><EFBFBD><EFBFBD>HSE */
rcc_osc_init.PLL.PLLState = RCC_PLL_ON; /* <20><><EFBFBD><EFBFBD>PLL */
rcc_osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; /* PLLʱ<4C><CAB1>Դѡ<D4B4><D1A1>HSE */
rcc_osc_init.PLL.PLLN = plln;
rcc_osc_init.PLL.PLLM = pllm;
rcc_osc_init.PLL.PLLP = pllp;
rcc_osc_init.PLL.PLLQ = pllq;
ret = HAL_RCC_OscConfig(&rcc_osc_init); /* <20><>ʼ<EFBFBD><CABC>RCC */
if(ret != HAL_OK)
{
return 1; /* ʱ<>ӳ<EFBFBD>ʼ<EFBFBD><CABC>ʧ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><D4BC>Ĵ<EFBFBD><C4B4><EFBFBD> */
}
/* ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HCLK,PCLK1<4B><31>PCLK2 */
rcc_clk_init.ClockType = ( RCC_CLOCKTYPE_SYSCLK \
| RCC_CLOCKTYPE_HCLK \
| RCC_CLOCKTYPE_PCLK1 \
| RCC_CLOCKTYPE_PCLK2);
rcc_clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* <20><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>ʱ<EFBFBD><CAB1>ԴΪPLL */
rcc_clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; /* AHB<48><42>Ƶϵ<C6B5><CFB5>Ϊ1 */
rcc_clk_init.APB1CLKDivider = RCC_HCLK_DIV4; /* APB1<42><31>Ƶϵ<C6B5><CFB5>Ϊ4 */
rcc_clk_init.APB2CLKDivider = RCC_HCLK_DIV2; /* APB2<42><32>Ƶϵ<C6B5><CFB5>Ϊ2 */
ret = HAL_RCC_ClockConfig(&rcc_clk_init, FLASH_LATENCY_5); /* ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>FLASH<53><48>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ϊ5WS<57><53>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD>6<EFBFBD><36>CPU<50><55><EFBFBD><EFBFBD> */
if(ret != HAL_OK)
{
return 1; /* ʱ<>ӳ<EFBFBD>ʼ<EFBFBD><CABC>ʧ<EFBFBD><CAA7> */
}
/* STM32F405x/407x/415x/417x Z<>汾<EFBFBD><E6B1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>Ԥȡ<D4A4><C8A1><EFBFBD><EFBFBD> */
if (HAL_GetREVID() == 0x1001)
{
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); /* ʹ<><CAB9>flashԤȡ */
}
return 0;
}
#ifdef USE_FULL_ASSERT
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>˺<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param file<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>Դ<EFBFBD>ļ<EFBFBD>
* line<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD>е<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void assert_failed(uint8_t* file, uint32_t line)
{
while (1)
{
}
}
#endif