182 lines
7.4 KiB
ArmAsm
182 lines
7.4 KiB
ArmAsm
;********************************************************************************************************
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; uC/CPU
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; CPU CONFIGURATION & PORT LAYER
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;
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; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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;
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; SPDX-License-Identifier: APACHE-2.0
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;
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; This software is subject to an open source license and is distributed by
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; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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;
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;********************************************************************************************************
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;********************************************************************************************************
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;
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; CPU PORT FILE
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;
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; ARM
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; IAR C Compiler
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;
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; Filename : cpu_a.s
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; Version : V1.32.01
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;********************************************************************************************************
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;********************************************************************************************************
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; PUBLIC FUNCTIONS
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;********************************************************************************************************
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PUBLIC CPU_SR_Save
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PUBLIC CPU_SR_Restore
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PUBLIC CPU_IntDis
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PUBLIC CPU_IntEn
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PUBLIC CPU_IRQ_Dis
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PUBLIC CPU_IRQ_En
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PUBLIC CPU_FIQ_Dis
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PUBLIC CPU_FIQ_En
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;********************************************************************************************************
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; EQUATES
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;********************************************************************************************************
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CPU_ARM_CTRL_INT_DIS EQU 0xC0 ; Disable both FIQ & IRQ
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CPU_ARM_CTRL_FIQ_DIS EQU 0x40 ; Disable FIQ.
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CPU_ARM_CTRL_IRQ_DIS EQU 0x80 ; Disable IRQ.
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;********************************************************************************************************
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; CODE GENERATION DIRECTIVES
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;********************************************************************************************************
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RSEG CODE:CODE:NOROOT(2)
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CODE32
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;********************************************************************************************************
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; CRITICAL SECTION FUNCTIONS
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;
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; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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;
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; Prototypes : CPU_SR CPU_SR_Save (void);
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; void CPU_SR_Restore(CPU_SR cpu_sr);
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;
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; Note(s) : (1) These functions are used in general like this :
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;
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; void Task (void *p_arg)
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; {
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; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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; :
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; :
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; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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; :
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; :
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; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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; :
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; }
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;
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; (2) CPU_SR_Restore() is implemented as recommended by Atmel's application note :
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;
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; "Disabling Interrupts at Processor Level"
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;********************************************************************************************************
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CPU_SR_Save
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MRS R0, CPSR
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CPU_SR_Save_Loop
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; Set IRQ & FIQ bits in CPSR to DISABLE all interrupts
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ORR R1, R0, #CPU_ARM_CTRL_INT_DIS
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MSR CPSR_c, R1
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MRS R1, CPSR ; Confirm that CPSR contains the proper interrupt disable flags
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AND R1, R1, #CPU_ARM_CTRL_INT_DIS
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CMP R1, #CPU_ARM_CTRL_INT_DIS
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BNE CPU_SR_Save_Loop ; NOT properly DISABLED (try again)
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BX LR ; DISABLED, return the original CPSR contents in R0
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CPU_SR_Restore ; See Note #2
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MSR CPSR_c, R0
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BX LR
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;********************************************************************************************************
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; ENABLE & DISABLE INTERRUPTS
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;
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; Description : Disable/Enable IRQs & FIQs.
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;
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; Prototypes : void CPU_IntEn (void);
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; void CPU_IntDis(void);
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;********************************************************************************************************
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CPU_IntDis
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MRS R0, CPSR
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ORR R0, R0, #CPU_ARM_CTRL_INT_DIS ; Set IRQ and FIQ bits in CPSR to disable all interrupts.
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MSR CPSR_c, R0
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BX LR
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CPU_IntEn
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MRS R0, CPSR
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BIC R0, R0, #CPU_ARM_CTRL_INT_DIS ; Clear IRQ and FIQ bits in CPSR to enable all interrupts.
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MSR CPSR_c, R0
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BX LR
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;********************************************************************************************************
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; ENABLE & DISABLE IRQs
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;
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; Description : Disable/Enable IRQs.
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;
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; Prototypes : void CPU_IRQ_En (void);
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; void CPU_IRQ_Dis(void);
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;********************************************************************************************************
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CPU_IRQ_Dis
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MRS R0, CPSR
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ORR R0, R0, #CPU_ARM_CTRL_IRQ_DIS ; Set IRQ bit in CPSR to disable IRQs.
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MSR CPSR_c, R0
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BX LR
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CPU_IRQ_En
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MRS R0, CPSR
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BIC R0, R0, #CPU_ARM_CTRL_IRQ_DIS ; Clear IRQ bit in CPSR to enable IRQs.
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MSR CPSR_c, R0
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BX LR
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;********************************************************************************************************
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; ENABLE & DISABLE FIQs
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;
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; Description : Disable/Enable FIQs.
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;
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; Prototypes : void CPU_FIQ_En (void);
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; void CPU_FIQ_Dis(void);
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;********************************************************************************************************
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CPU_FIQ_Dis
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MRS R0, CPSR
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ORR R0, R0, #CPU_ARM_CTRL_FIQ_DIS ; Set FIQ bit in CPSR to disable FIQs.
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MSR CPSR_c, R0
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BX LR
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CPU_FIQ_En
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MRS R0, CPSR
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BIC R0, R0, #CPU_ARM_CTRL_FIQ_DIS ; Clear FIQ bit in CPSR to enable FIQs.
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MSR CPSR_c, R0
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BX LR
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;********************************************************************************************************
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; CPU ASSEMBLY PORT FILE END
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;********************************************************************************************************
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END
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