143 lines
6.1 KiB
ArmAsm
143 lines
6.1 KiB
ArmAsm
/*
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*********************************************************************************************************
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* uC/CPU
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* CPU CONFIGURATION & PORT LAYER
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*
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* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* CPU PORT FILE
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*
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* MIPS32 4K
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* MPLAB
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*
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* Filename : cpu_a.s
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* Version : V1.32.01
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* PUBLIC FUNCTIONS
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*********************************************************************************************************
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*/
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.global CPU_SR_Save
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.global CPU_SR_Restore
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.global CPU_CntLeadZeros
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/*
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*********************************************************************************************************
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* CODE GENERATION DIRECTIVES
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*********************************************************************************************************
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*/
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.section .text,code
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.set noreorder
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/*
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**********************************************************************************************************
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* CRITICAL SECTION FUNCTIONS
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*
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* Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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* state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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* are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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* The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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*
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* Prototypes : CPU_SR CPU_SR_Save(void);
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* void CPU_SR_Restore(CPU_SR cpu_sr);
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**********************************************************************************************************
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*/
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.ent CPU_SR_Save
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CPU_SR_Save:
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di $2 /* Disable interrupts, and move the old value of the... */
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jr.hb $31 /* ...Status register into v0 ($2) */
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nop
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.end CPU_SR_Save
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.ent CPU_SR_Restore
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CPU_SR_Restore:
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mtc0 $4, $12, 0 /* Restore the status register to its previous state */
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jr.hb $31
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nop
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.end CPU_SR_Restore
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/*
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*********************************************************************************************************
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* CPU_CntLeadZeros()
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*
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* Description : Count the number of contiguous, most-significant, leading zero bits in a data value.
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*
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* Argument(s) : val Data value to count leading zero bits.
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*
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* Return(s) : Number of contiguous, most-significant, leading zero bits in 'val', if NO error(s).
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* 0, otherwise.
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*
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* Note(s) : (1) (a) Supports the following data value sizes :
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*
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* (1) 8-bits - N/A
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* (2) 16-bits - N/A
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* (3) 32-bits - M4K core (see MIPS clz documentation)
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* (4) 64-bits - N/A
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*
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* See also 'cpu_def.h CPU WORD CONFIGURATION Note #1'.
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*
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*
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* (3) For 32-bit values :
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*
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* b31 b30 b29 ... b04 b03 b02 b01 b00 # Leading Zeros
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* --- --- --- --- --- --- --- --- ---------------
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* 1 x x x x x x x 0
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* 0 1 x x x x x x 1
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* 0 0 1 x x x x x 2
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* : : : : : : : : :
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* : : : : : : : : :
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* 0 0 0 1 x x x x 27
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* 0 0 0 0 1 x x x 28
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* 0 0 0 0 0 1 x x 29
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* 0 0 0 0 0 0 1 x 30
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* 0 0 0 0 0 0 0 1 31
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* 0 0 0 0 0 0 0 0 32
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*
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*
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*
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* Note(s) : (1) This functions is used when CPU_CFG_LEAD_ZEROS_ASM_PRESENT is defined in cpu.h/cpu_cfg.h.
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* This function has been implemented to use the Count Leading Zeros (CLZ) instruction
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* present in the M4K core.
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* (2) This function was located here because it is hardware dependant, and is part of the port.
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* The function prototype exists in cpu.h. It is needed because this assembler routine is
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* called from C.
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* (3) See MIPS documentation for explanation of why the same GP register is used for source and
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* desitination of the clz instruction.
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*********************************************************************************************************
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*/
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.ent CPU_CntLeadZeros
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CPU_CntLeadZeros:
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clz $4, $4 /* Count leading zeros in value passed into GP $4 */
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jr $31
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addu $2, $4, $0 /* Result is returned to caller in GP $2 */
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.end CPU_CntLeadZeros
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