128 lines
5.1 KiB
ArmAsm
128 lines
5.1 KiB
ArmAsm
#********************************************************************************************************
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#* uC/CPU
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#* CPU CONFIGURATION & PORT LAYER
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#*
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#* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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#*
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#* SPDX-License-Identifier: APACHE-2.0
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#*
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#* This software is subject to an open source license and is distributed by
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#* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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#* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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#*
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#********************************************************************************************************
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#********************************************************************************************************
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#
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# CPU PORT FILE
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#
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# V850ES
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# Renesas CA850
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#
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# Filename : cpu_a.s
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# Version : V1.32.01
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#********************************************************************************************************
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#********************************************************************************************************
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# PUBLIC FUNCTIONS
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#********************************************************************************************************
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.extern _CPU_SR_Save
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.extern _CPU_SR_Restore
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.extern _CPU_IntDis
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.extern _CPU_IntEn
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.extern _CPU_ECR_Rd
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#********************************************************************************************************
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# EQUATES
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#********************************************************************************************************
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.set ECR, 4
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.set PSW, 5
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#********************************************************************************************************
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# CODE GENERATION DIRECTIVES
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#********************************************************************************************************
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.text
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.align 4
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#********************************************************************************************************
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# SAVE/RESTORE CPU STATUS REGISTER
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#
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# Description : Save/Restore the state of CPU interrupts, if possible.
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#
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# (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
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# stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
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# allocated in all functions that need to disable interrupts). The previous interrupt
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# status state is restored by copying 'cpu_sr' into the CPU's status register.
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#
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#
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# Prototypes : CPU_SR CPU_SR_Save (void);
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# void CPU_SR_Restore(CPU_SR cpu_sr);
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#
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# Note(s) : (1) These functions are used in general like this :
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#
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# void Task (void *p_arg)
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# {
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# CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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# :
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# :
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# CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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# :
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# :
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# CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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# :
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# }
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#********************************************************************************************************
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_CPU_SR_Save:
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stsr PSW, r10 -- Store PSW
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di
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jmp [lp]
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_CPU_SR_Restore:
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ldsr r6 , PSW
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jmp [lp]
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#********************************************************************************************************
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# DISABLE and ENABLE INTERRUPTS
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#
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# Description: Disable/Enable interrupts.
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#
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# Prototypes : void CPU_IntDis(void);
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# void CPU_IntEn (void);
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#********************************************************************************************************
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_CPU_IntDis:
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di
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jmp [lp]
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_CPU_IntEn:
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ei
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jmp [lp]
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#********************************************************************************************************
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# READS CPU EXCEPTION CAUSE REGISTER
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#
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# Description : Reads CPU exception code register(ECR), which identifies each interrupt source according to
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# its exception code.
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#
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# Prototypes : CPU_DATA CPU_ECR_Rd (void);
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#
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# Note(s) : None.
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#
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#********************************************************************************************************
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_CPU_ECR_Rd:
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stsr ECR, r10
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jmp [lp]
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#********************************************************************************************************
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# CPU ASSEMBLY PORT FILE END
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#********************************************************************************************************
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