425 lines
14 KiB
C
425 lines
14 KiB
C
#include "drv_clk.h"
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#include "drv_can.h"
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#include "drv_gpio.h"
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#include "drv_misc.h"
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#include "kit_debug.h"
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#define CAN_INIT_TIMEOUT (0xFFF0u)
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#define CAN_SJW_1tq (0u)
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#define CAN_BS2_1tq (0u)
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#define CAN_BS2_2tq (1u)
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#define CAN_BS1_4tq (3u)
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#define CAN_BS1_6tq (5u)
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#define CAN_BS1_13tq (12u)
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#define CAN_BS1_16tq (15u)
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#define CAN_RTR_DATA (0u)
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#define GPIO_REMAP1_CAN1 ((uint32_t)0x00004000)
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#define GPIO_REMAP2_CAN1 ((uint32_t)0x00006000)
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#define GPIO_REMAP_CAN2 ((uint32_t)0x00400000)
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typedef struct
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{
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uint8_t irq[kCanInterrupt_End];
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CAN_TypeDef* reg;
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}Stm32CanProp;
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static KitResult drv_can_set_clock_gpio(CanDev dev, uint16_t rx_io, uint16_t tx_io);
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static KitIrqCall can_irq_call[kCanDev_End][kCanInterrupt_End];
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static const Stm32CanProp stm32_can[kCanDev_End] =
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{
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#if defined(STM32F10X_CL) || defined(STM32F40_41xxx) || defined(STM32F429_439xx)
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{{CAN1_RX0_IRQn, CAN1_TX_IRQn}, CAN1},
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{{CAN2_RX0_IRQn, CAN2_TX_IRQn}, CAN2},
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#else
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{{USB_LP_CAN1_RX0_IRQn, USB_HP_CAN1_TX_IRQn}, CAN1},
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#endif
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};
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const uint8_t can_mailbox_tab[8] = {0xFF, 0, 1, 0, 2, 0, 1, 0};
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uint8_t drv_can_get_mailbox(CanDev dev)
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{
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uint8_t mailbox = 0xFF;
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KIT_ASSERT_PARAM(dev < kCanDev_End);
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if(dev < kCanDev_End)
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mailbox = can_mailbox_tab[(stm32_can[dev].reg->TSR >> 26) & 0x07];
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return mailbox;
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}
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KitResult drv_can_send(CanDev dev, CanMsg *msg)
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{
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uint8_t id_move = 3, mailbox;
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KitResult res = kKitResult_ParamErr;
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CAN_TypeDef *can_reg;
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KIT_ASSERT_PARAM(msg != NULL);
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KIT_ASSERT_PARAM(dev < kCanDev_End);
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if((dev < kCanDev_End) && (msg != NULL))
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{
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can_reg = stm32_can[dev].reg;
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mailbox = can_mailbox_tab[(can_reg->TSR >> 26) & 0x07];
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if (mailbox != 0xFF)
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{
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if (msg->ide == kCanIde_Std)
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{
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id_move = 21;
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}
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//write identifier
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can_reg->sTxMailBox[mailbox].TIR = (msg->id.value << id_move) | (msg->ide << 2) | (msg->rtr << 1);
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//write length
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can_reg->sTxMailBox[mailbox].TDTR = msg->len & 0x0F;
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//write data
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can_reg->sTxMailBox[mailbox].TDLR = msg->data.value[0];
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can_reg->sTxMailBox[mailbox].TDHR = msg->data.value[1];
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//request send
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can_reg->sTxMailBox[mailbox].TIR |= 0x00000001;
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res = kKitResult_Ok;
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}
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else
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{
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res = kKitResult_OverFlow;
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}
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}
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return res;
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}
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KitResult drv_can_receive(CanDev dev, CanMsg* msg)
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{
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KitResult res = kKitResult_ParamErr;
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CAN_FIFOMailBox_TypeDef fifo;
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KIT_ASSERT_PARAM(msg != NULL);
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KIT_ASSERT_PARAM(dev < kCanDev_End);
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if((dev < kCanDev_End) && (msg != NULL))
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{
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fifo = stm32_can[dev].reg->sFIFOMailBox[0];
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/* Get the Id */
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msg->rtr = (CanRtr)(0x00000001 & fifo.RIR >> 1);
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msg->ide = (CanIde)(0x00000001 & fifo.RIR >> 2);
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if (msg->ide == kCanIde_Std)
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msg->id.value = (uint32_t)0x000007FF & (fifo.RIR >> 21);
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else
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msg->id.value = (uint32_t)0x1FFFFFFF & (fifo.RIR >> 3);
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msg->len = (uint8_t)0x0F & fifo.RDTR;
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msg->data.value[0] = fifo.RDLR;
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msg->data.value[1] = fifo.RDHR;
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/* Release the FIFO */
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stm32_can[dev].reg->RF0R |= CAN_RF0R_RFOM0;
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res = kKitResult_Ok;
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}
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return res;
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}
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/**********************************************************************************
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* Func CAN1_REMAP0 CAN1_REMAP1 CAN1_REMAP2 CAN2_REMAP0 CAN2_REMAP1
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* CAN_RX PA11 PB8 PD0 PB12 PB5
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* CAN_TX PA12 PB9 PD1 PB13 PB6
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**********************************************************************************/
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static KitResult drv_can_set_clock_gpio(CanDev dev, uint16_t rx_idx, uint16_t tx_idx)
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{
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KitResult res = kKitResult_Ok;
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uint32_t rx_io = drv_gpio_get_actual_io(rx_idx);
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uint32_t tx_io = drv_gpio_get_actual_io(tx_idx);
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switch (dev)
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{
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case kCanDev_1:
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RCC->APB1ENR |= RCC_APB1Periph_CAN1;
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if((rx_io == GPIO_PORT_PIN(kGpioPort_A, 11)) && (tx_io == GPIO_PORT_PIN(kGpioPort_A, 12)))
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{
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drv_gpio_set_af(kGpioPort_A, 11, 9);
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drv_gpio_set_af(kGpioPort_A, 12, 9);
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}
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else if((rx_io == GPIO_PORT_PIN(kGpioPort_B, 8)) && (tx_io == GPIO_PORT_PIN(kGpioPort_B, 9)))
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{
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drv_gpio_set_af(kGpioPort_B, 8, 9);
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drv_gpio_set_af(kGpioPort_B, 9, 9);
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}
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else if((rx_io == GPIO_PORT_PIN(kGpioPort_D, 0)) && (tx_io == GPIO_PORT_PIN(kGpioPort_D, 1)))
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{
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drv_gpio_set_af(kGpioPort_D, 0, 9);
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drv_gpio_set_af(kGpioPort_D, 1, 9);
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}
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else
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res = kKitResult_ParamErr;
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break;
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#if defined(STM32F10X_CL) || defined(STM32F40_41xxx) || defined(STM32F429_439xx)
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//使用CAN2接收需要使能CAN1时钟
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case kCanDev_2:
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RCC->APB1ENR |= RCC_APB1Periph_CAN1;
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RCC->APB1ENR |= RCC_APB1Periph_CAN2;
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if((rx_io == GPIO_PORT_PIN(kGpioPort_B, 12)) && (tx_io == GPIO_PORT_PIN(kGpioPort_B, 13)))
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{
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drv_gpio_set_af(kGpioPort_B, 12, 9);
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drv_gpio_set_af(kGpioPort_B, 13, 9);
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}
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else if((rx_io == GPIO_PORT_PIN(kGpioPort_B, 5)) && (tx_io == GPIO_PORT_PIN(kGpioPort_B, 6)))
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{
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drv_gpio_set_af(kGpioPort_B, 5, 9);
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drv_gpio_set_af(kGpioPort_B, 6, 9);
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}
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else
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res = kKitResult_ParamErr;
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break;
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#endif
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default:
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res = kKitResult_ParamErr;
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break;
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}
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return res;
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}
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//默认全部关联到FIFO0
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void can_set_list_filter(uint8_t channel, CanIde ide, CanRtr rtr, uint32_t rcv_id1, uint32_t rcv_id2)
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{
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uint8_t id_move = 3;
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uint32_t bit;
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KIT_ASSERT_PARAM(channel < 28);
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KIT_ASSERT_PARAM(ide < kCanIde_End);
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KIT_ASSERT_PARAM(rtr < kCanRtr_End);
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bit = KIT_CREAT_BIT(channel);
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CAN1->FMR |= CAN_FMR_FINIT; //进入CAN配置模式
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CAN1->FM1R |= bit; //列表模式
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CAN1->FS1R |= bit; //32位数据长度
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id_move = 3;
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if(ide == kCanIde_Std)
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{
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id_move = 21;
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}
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CAN1->sFilterRegister[channel].FR1 = (rcv_id1 << id_move) | (ide << 2) | (rtr << 1);
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CAN1->sFilterRegister[channel].FR2 = (rcv_id2 << id_move) | (ide << 2) | (rtr << 1);
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CAN1->FA1R |= bit;
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CAN1->FMR &= ~CAN_FMR_FINIT;
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}
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//屏蔽位模式 0不关心 1必须匹配
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void can_set_mask_filter(uint8_t channel, CanIde ide, CanRtr rtr, uint32_t rcv_id, uint32_t mask_id)
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{
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uint8_t id_move;
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uint32_t bit;
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KIT_ASSERT_PARAM(channel < 28);
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KIT_ASSERT_PARAM(ide < kCanIde_End);
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KIT_ASSERT_PARAM(rtr < kCanRtr_End);
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bit = KIT_CREAT_BIT(channel);
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CAN1->FMR |= CAN_FMR_FINIT; //进入CAN配置模式
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CAN1->FM1R &= ~bit; //屏蔽模式
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CAN1->FS1R |= bit; //32位数据长度
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id_move = 3;
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if(ide == kCanIde_Std)
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{
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id_move = 21;
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}
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CAN1->sFilterRegister[channel].FR1 = (rcv_id << id_move) | (ide << 2) | CAN_RTR_DATA;
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CAN1->sFilterRegister[channel].FR2 = (mask_id << id_move) | (ide << 2) | CAN_RTR_DATA;
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CAN1->FA1R |= bit;
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CAN1->FMR &= ~CAN_FMR_FINIT;
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}
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/*----------------------------------------STM32F10x MCR(master control register)寄存器---------------------------------------------------
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| Bit | 16 | 15 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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-----------------------------------------------------------------------------------------------------------------------------------------
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| Item | DBF | RESET | TTCM | ABOM | AWUM | NART | RFLM | TXFP | SLEEP | INRQ |
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-----------------------------------------------------------------------------------------------------------------------------------------
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| DEF | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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-----------------------------------------------------------------------------------------------------------------------------------------
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| Value |1 调试时冻结 |0 不复位 |0 禁用时间触发模式|1 硬件控制Buf off|1 硬件唤醒|0 自动重发|1 满停止接收|1 按顺序发送| | |
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*软件通过置位SLEEP来请求进入睡眠模式，置位后CAN在当前活动完成后将立即进入睡眠模式，当AWUM置位后，也可以被硬件唤醒清零
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*CAN波特率=APB总线频率/BRP分频器/(1+tBS1+tBS2) 5kbps = 42000/900/(1+6+1)
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*波特率必须是5kbps倍数,小于500，以36M的APB1Periph时钟频率计算，5kbps时在(SJW_1tq, BS1_6tq, BS2_1tq)预分频为900, 其他波特率分频计算 900 / (baud_rate/5)
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*使用CAN2必须使能CAN1时钟
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*CAN初始化同步到总线使用时间根据情况而定，设备较多，有报文需要等待的时间较长
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*本驱动只使用FIFO0，滤波器都关联到FIFO0
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*CAN1过滤器起始地址为0，共有14个，CAN2为14共有14个
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*0表示不过滤，1表示对应位要过滤
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*配置过滤器时必须处于初始化模式
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----------------------------------------------------------------------------------------------------------------------------------------*/
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KitResult drv_can_init(CanDev dev, uint32_t baud_rate, uint16_t rx_io, uint16_t tx_io)
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{
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uint32_t tmp;
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KitResult res;
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CAN_TypeDef *can_reg;
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KIT_ASSERT_PARAM(dev < kCanDev_End);
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KIT_ASSERT_PARAM(((baud_rate % 5) == 0) && (baud_rate <= 500));
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res = drv_can_set_clock_gpio(dev, rx_io, tx_io);
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if(res == kKitResult_Ok)
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{
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can_reg = stm32_can[dev].reg;
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// leave sleep mode
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can_reg->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
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// request init mode
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can_reg->MCR |= CAN_MCR_INRQ ;
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// wait init acknowledge
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res |= kit_wait_flag(&can_reg->MSR, CAN_MSR_INAK, CAN_INIT_TIMEOUT);
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//cfg main register 自动退出离线 | 多个报文同时等待发送由请求顺序决定 | 自动重发
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tmp = (CAN_MCR_ABOM | CAN_MCR_TXFP | CAN_MCR_RFLM);
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can_reg->MCR |= tmp;
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//Baud rate prescaler BRP = CLOCK_PCLK1_FREQ / (SJW + BS1 + BS2) / baud_rate - 1
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switch(baud_rate)
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{
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case 125:
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case 250:
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can_reg->BTR = ((uint32_t)CAN_SJW_1tq << 24) | ((uint32_t)CAN_BS1_6tq << 16) | ((uint32_t)CAN_BS2_1tq << 20) | (CLOCK_PCLK1_FREQ / 8000 / baud_rate - 1);
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break;
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case 500:
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case 1000:
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can_reg->BTR = ((uint32_t)CAN_SJW_1tq << 24) | ((uint32_t)CAN_BS1_4tq << 16) | ((uint32_t)CAN_BS2_1tq << 20) | (CLOCK_PCLK1_FREQ / 6000 / baud_rate - 1);
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break;
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default:
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can_reg->BTR = ((uint32_t)CAN_SJW_1tq << 24) | ((uint32_t)CAN_BS1_6tq << 16) | ((uint32_t)CAN_BS2_1tq << 20) | (CLOCK_PCLK1_FREQ / 8000 / 250 - 1);
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break;
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}
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//leave init mode
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can_reg->MCR &= ~(uint32_t)CAN_MCR_INRQ;
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// Wait the normal acknowledge,当总线有报文时等待时间会较长
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res |= kit_wait_flag(&can_reg->MSR, CAN_MSR_INAK, CAN_INIT_TIMEOUT);
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//默认接收任何ID的扩展帧和标准帧
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dev *= 14; //通道2起始过滤器为14
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CAN1->FMR |= CAN_FMR_FINIT; //进入CAN配置模式
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CAN1->FM1R = 0; //所有过滤器组工作在屏蔽位模式
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CAN1->FA1R |= KIT_CREAT_BIT(dev);
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CAN1->sFilterRegister[dev].FR1 = 0; //所有位不关心
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CAN1->sFilterRegister[dev].FR2 = 0;
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CAN1->FMR &= ~CAN_FMR_FINIT;
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}
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KIT_ASSERT_RES(dev, res);
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return res;
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}
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const uint8_t can_interrupt_bit[kCanInterrupt_End] = {0x02, 0x01};
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KitResult drv_can_set_interrupt(CanDev dev, CanInterrupt it_type, uint16_t priority, KitIrqCall call)
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{
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KitResult res;
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KIT_ASSERT_PARAM((dev < kCanDev_End) && (it_type < kCanInterrupt_End) && (call != NULL));
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if((dev < kCanDev_End) && (it_type < kCanInterrupt_End) && (call != NULL))
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{
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can_irq_call[dev][it_type] = call;
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drv_misc_set_nvic(stm32_can[dev].irq[it_type], priority);
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stm32_can[dev].reg->IER |= can_interrupt_bit[it_type];
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res = kKitResult_Ok;
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}
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else
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{
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res = kKitResult_ParamErr;
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}
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return res;
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}
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KitResult drv_can_ctrl_interrupt(CanDev dev, CanInterrupt it_type, bool is_enable)
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{
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KitResult res;
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KIT_ASSERT_PARAM((dev < kCanDev_End) && (it_type < kCanInterrupt_End));
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if((dev < kCanDev_End) && (it_type < kCanInterrupt_End))
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{
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if (is_enable == true)
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stm32_can[dev].reg->IER |= can_interrupt_bit[it_type];
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else
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stm32_can[dev].reg->IER &= ~can_interrupt_bit[it_type];
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res = kKitResult_Ok;
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}
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else
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{
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res = kKitResult_ParamErr;
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}
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return res;
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}
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void drv_can_rx_irq_handler(CanDev dev)
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{
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CanMsg msg;
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if(can_irq_call[dev][kCanInterrupt_Rx] != NULL)
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{
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while((stm32_can[dev].reg->RF0R & 0x03) != 0)
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{
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drv_can_receive(dev, &msg);
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can_irq_call[dev][kCanInterrupt_Rx](kKitResult_Ok, &msg);
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}
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}
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else
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{
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//清除中断标志，防止一直进中断
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stm32_can[dev].reg->RF0R |= CAN_RF0R_RFOM0;
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}
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}
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void drv_can_tx_irq_handler(CanDev dev)
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{
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stm32_can[dev].reg->TSR |= 0x00010101;
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if(can_irq_call[dev][kCanInterrupt_Tx] != NULL)
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{
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can_irq_call[dev][kCanInterrupt_Tx](kKitResult_Ok, NULL);
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}
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}
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void CAN1_RX0_IRQHandler(void)
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{
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drv_can_rx_irq_handler(kCanDev_1);
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}
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void CAN1_TX_IRQHandler (void)
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{
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drv_can_tx_irq_handler(kCanDev_1);
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}
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#if defined(STM32F10X_CL) || defined(STM32F40_41xxx) || defined(STM32F429_439xx)
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void CAN2_RX0_IRQHandler(void)
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{
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drv_can_rx_irq_handler(kCanDev_2);
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}
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void CAN2_TX_IRQHandler (void)
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{
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drv_can_tx_irq_handler(kCanDev_2);
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}
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#endif
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