124 lines
4.9 KiB
ArmAsm
124 lines
4.9 KiB
ArmAsm
#********************************************************************************************************
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# uC/CPU
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# CPU CONFIGURATION & PORT LAYER
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#
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# Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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#
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# SPDX-License-Identifier: APACHE-2.0
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#
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# This software is subject to an open source license and is distributed by
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# Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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# Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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#
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#********************************************************************************************************
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#********************************************************************************************************
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#
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# CPU PORT FILE
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#
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# RISC-V
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# GNU C Compiler
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#
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# Filename : cpu_a.S
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# Version : V1.32.01
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#********************************************************************************************************
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#********************************************************************************************************
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# PUBLIC FUNCTIONS
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#********************************************************************************************************
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.global CPU_SR_Save
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.global CPU_SR_Restore
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.global CPU_IntDis
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.global CPU_IntEn
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#********************************************************************************************************
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# EQUATES
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#********************************************************************************************************
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.equ CPU_MSTATUS_MIE, 0x08
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#********************************************************************************************************
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# CODE GENERATION DIRECTIVES
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#********************************************************************************************************
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.section .text
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#********************************************************************************************************
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# DISABLE/ENABLE INTERRUPTS
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#
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# Description : Disable/Enable interrupts.
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#
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# (1) (a) For CPU_CRITICAL_METHOD_INT_DIS_EN, interrupts are enabled/disabled WITHOUT saving
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# or restoring the state of the interrupt status.
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#
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#
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# Prototypes : void CPU_IntDis(void);
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# void CPU_IntEn (void);
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#********************************************************************************************************
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CPU_IntDis:
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# Disable global interupt
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li t0, CPU_MSTATUS_MIE
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csrrc zero, mstatus, t0
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ret
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CPU_IntEn:
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# Enable global interupt
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li t0, CPU_MSTATUS_MIE
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csrrs zero, mstatus, t0
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ret
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#********************************************************************************************************
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# CRITICAL SECTION FUNCTIONS
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#
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# Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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# state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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# are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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# The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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#
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# Prototypes : CPU_SR CPU_SR_Save (void);
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# void CPU_SR_Restore(CPU_SR cpu_sr);
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#
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# Note(s) : (1) These functions are used in general like this :
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#
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# void Task (void *p_arg)
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# {
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# CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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# :
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# :
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# CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save()# */
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# :
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# :
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# CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr)# */
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# :
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# }
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#********************************************************************************************************
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CPU_SR_Save:
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# Save the Machine status register
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csrr a0, mstatus
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# Disable global interupt
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li t0, CPU_MSTATUS_MIE
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csrrc zero, mstatus, t0
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ret
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CPU_SR_Restore:
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# restore the Machine status register previous state
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csrw mstatus, a0
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ret
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#********************************************************************************************************
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# CPU ASSEMBLY PORT FILE END
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#********************************************************************************************************
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