156 lines
4.9 KiB
C
156 lines
4.9 KiB
C
#include "drv_clk.h"
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#include "drv_misc.h"
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#include "kit_debug.h"
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#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
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#define NVIC_PriorityGroup_0 ((uint32_t)0x700)
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#define GPIO_REMAP_EN_SWO_DIS_JTAG ((uint32_t)0x02000000)
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/***********************************************************
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*HSI是高速内部时钟，RC振荡器，频率为8MHz。
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*HSE是高速外部时钟，可接石英/陶瓷谐振器，或者接外部时钟源，频率范围为4MHz~16MHz。
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*LSI是低速内部时钟，RC振荡器，频率为40kHz。
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*LSE是低速外部时钟，接频率为32.768kHz的石英晶体。
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*PLL为锁相环倍频输出，其时钟输入源可选择为HSI/2、HSE或者HSE/2。倍频可选择为2~16倍
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*FCLK,提供给CPU内核的时钟信号,CPU的主频就是指这个信号;
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*HCLK,提供给高速总线AHB的时钟信号;
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*PCLK,提供给低速总线APB的时钟信号;
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*SYSCLK,系统时钟，最大72MHz
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*HSE(8M)->PLLXTPRE(*1)->PLLSRC(HSE)->PLLMUL(*9)->SW(PLL)
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*互联型 HSE(8M)->PREDIV1SCR(HSE)->PLLSRC(/1)->PLLMUL(*9) -> SW (PLL)
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***********************************************************/
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void drv_clk_init(void)
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{
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// uint16_t dly = 500;
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//#ifndef STM32F10X_CL
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// RCC->CFGR &= (uint32_t)0xF8FF0000;
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//#else
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// RCC->CFGR &= (uint32_t)0xF0FF0000;
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//#endif
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// SCB->VTOR = APP_START_ADDR;
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// /* Enable HSE */
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// RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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//
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// while((RCC->CR & RCC_CR_HSERDY) == 0)
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// {
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// if(dly-- < 1)
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// KIT_ASSERT_RES(0, kKitResult_Error);
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// }
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// /* Enable Prefetch Buffer */
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// FLASH->ACR |= FLASH_ACR_PRFTBE;
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// /* Flash 2 wait state */
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// FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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// FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
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// /* HCLK = SYSCLK */
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// RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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// /* PCLK2 = HCLK */
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// RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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// /* PCLK1 = HCLK */
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// RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
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// /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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// RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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//#ifdef STM32F10X_CL
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// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9);
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//#else
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// RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
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//#endif
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// /* Enable PLL */
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// RCC->CR |= RCC_CR_PLLON;
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// dly = 0xFFFF;
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// /* Wait till PLL is ready */
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// while((RCC->CR & RCC_CR_PLLRDY) == 0)
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// {
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// if(dly-- < 1)
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// KIT_ASSERT_RES(0, kKitResult_Error);
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// }
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//
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// /* Select PLL as system clock source */
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// RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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// RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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// dly = 0xFFFF;
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// /* Wait till PLL is used as system clock source */
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// while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
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// {
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// if(dly-- < 1)
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// KIT_ASSERT_RES(0, kKitResult_Error);
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// }
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// //关闭抢占优先级
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// SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup_0;
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// //打开复用时钟
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// RCC->APB2ENR |= RCC_APB2Periph_AFIO;
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// //PB3 PB4作为普通IO
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// AFIO->MAPR |= GPIO_REMAP_EN_SWO_DIS_JTAG;
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}
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KitResult drv_clk_set_status(BspClkType clk, uint32_t dev)
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{
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KitResult res = kKitResult_Ok;
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// if(clk == kBspClk_AHB)
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// RCC->AHBENR |= dev;
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// else if(clk == kBspClk_APB1)
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// {
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// RCC->APB1ENR |= dev;
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// RCC->APB1RSTR |= dev;
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// RCC->APB1RSTR &= ~dev;
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// }
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// else if(clk == kBspClk_APB2)
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// {
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// RCC->APB2ENR |= dev;
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// RCC->APB2RSTR |= dev;
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// RCC->APB2RSTR &= ~dev;
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// }
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// else
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// {
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// res = kKitResult_ParamErr;
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// }
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return res;
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}
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NoArgCall systick_int_call;
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KitResult drv_clk_set_system_tick(uint8_t priority, uint16_t period, NoArgCall call)
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{
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uint32_t tick;
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KitResult res;
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KIT_ASSERT_PARAM((call != NULL) && (CLOCK_SYS_FREQ / 1000 * period) < SysTick_LOAD_RELOAD_Msk);
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tick = CLOCK_SYS_FREQ / 1000 * period;
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if ((call != NULL) && (tick < SysTick_LOAD_RELOAD_Msk))
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{
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systick_int_call = call;
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SysTick->LOAD = (tick & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
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drv_misc_set_nvic(SysTick_IRQn, priority); /* set Priority for Cortex-M0 System Interrupts */
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SysTick->VAL = 0; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_TICKINT_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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res = kKitResult_Ok;
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}
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else
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{
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res = kKitResult_ParamErr;
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}
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return res;
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}
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void SysTick_Handler(void)
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{
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KIT_ASSERT_PARAM(systick_int_call != NULL);
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systick_int_call();
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}
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