81 lines
3.5 KiB
NASM
81 lines
3.5 KiB
NASM
;********************************************************************************************************
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; uC/CPU
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; CPU CONFIGURATION & PORT LAYER
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;
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; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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;
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; SPDX-License-Identifier: APACHE-2.0
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;
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; This software is subject to an open source license and is distributed by
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; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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;
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;********************************************************************************************************
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;********************************************************************************************************
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;
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; CPU PORT FILE
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;
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; Fujitsu FR
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; Softune Compiler
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;
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; Filename : cpu_a.asm
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; Version : V1.32.01
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;********************************************************************************************************
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.PROGRAM CPU_A
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;********************************************************************************************************
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; PUBLIC FUNCTIONS
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;********************************************************************************************************
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.EXPORT _CPU_SR_Save
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.EXPORT _CPU_SR_Restore
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.section CODE, code, align=4
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;********************************************************************************************************
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; CRITICAL SECTION FUNCTIONS
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;
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; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
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; would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
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; disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
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; into the CPU's status register.
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;
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; Prototypes : CPU_SR CPU_SR_Save (void);
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; void CPU_SR_Restore(CPU_SR cpu_sr);
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;
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; Note(s) : (1) These functions are used in general like this :
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;
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; void Task (void *p_arg)
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; {
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; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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; :
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; :
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; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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; :
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; :
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; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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; :
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; }
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;********************************************************************************************************
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_CPU_SR_Save:
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MOV PS, R4 ; Save state of PS
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ANDCCR #0xEF ; Disable interrupts
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RET
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_CPU_SR_Restore:
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MOV R4, PS ; Restore state of PS
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RET
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;********************************************************************************************************
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; CPU ASSEMBLY PORT FILE END
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;********************************************************************************************************
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.END
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