[ADD] ADS8688 Driver
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guzz
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3bc41217d8
commit
7ac4bcd37b
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#include "ads8688.h"
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#include "drv_spi.h"
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#include "gpio_manager.h"
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void ads8688_write_command_reg(uint16_t command)
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{
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uint8_t command_data[2] = {0, 0};
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command_data[0] = (uint8_t) (command >> 8);
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command_data[1] = (uint8_t) (command & 0x00FF);
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drv_spi_sync_send_receive(kSpiDev_2, command_data);
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}
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void ads8688_write_program_reg(uint8_t addr, uint8_t data)
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{
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uint8_t w_data[2] = {0, 0};
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w_data[0] = (addr < 1) | 0x01;
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w_data[1] = data;
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drv_spi_sync_send_receive(kSpiDev_2, w_data);
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}
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void ads8688_read_program_reg(uint8_t addr)
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{
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uint8_t r_data[2] = {0, 0};
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uint8_t RxBuff;
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r_data[0] = (addr < 1);
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drv_spi_series_sync_send_receive(kSpiDev_2, r_data, 2, &RxBuff, 1);
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}
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void ads8688_enter_auto_rst_mode()
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{
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ads8688_write_command_reg(AUTO_RST);
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}
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void ads8688_set_autoscan_sequence(uint8_t data)
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{
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ads8688_write_program_reg(AUTO_SEQ_EN, data);
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}
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void ads8688_set_ch_range_select(uint8_t ch, uint8_t range)
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{
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ads8688_write_program_reg(ch, range);
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}
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void ads8688_set_channel_power_down(uint8_t pwd)
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{
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ads8688_write_program_reg(Channel_Power_Down, pwd);
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}
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short ads8688_adc_data_convert(uint16_t x, uint8_t AI_RANGE)
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{
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short y;
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switch(AI_RANGE) {
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case 0:
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y = x * 15625 / 100000; //channel range 0~10.24V
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break;
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case 1:
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y = x * 78125 / 1000000; //channel range 0~5.12V
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break;
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case 2:
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y = (x - 0x8000) * 3125 / 10000; //channel range 10.24V
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break;
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case 3:
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y = (uint16_t)(((double)(x - 32768) * 10.24 / (double)65535) * 1000); //channel range 5.12V
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break;
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case 4:
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y = (uint16_t)(((double)(x - 32768) * 5.12 / (double)65535) * 1000); //channel range 2.56V
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break;
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}
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return y;
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}
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uint16_t adc_data[8];
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uint16_t adc_real[8];
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void ads8688_get_real_adc_data(uint16_t *adc_real, uint8_t AI_RANGE)
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{
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adc_real[0] = (uint16_t)ads8688_adc_data_convert(adc_data[0], AI_RANGE);
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adc_real[1] = (uint16_t)ads8688_adc_data_convert(adc_data[1], AI_RANGE);
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adc_real[2] = (uint16_t)ads8688_adc_data_convert(adc_data[2], AI_RANGE);
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adc_real[3] = (uint16_t)ads8688_adc_data_convert(adc_data[3], AI_RANGE);
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adc_real[4] = (uint16_t)ads8688_adc_data_convert(adc_data[4], AI_RANGE);
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adc_real[5] = (uint16_t)ads8688_adc_data_convert(adc_data[5], AI_RANGE);
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adc_real[6] = (uint16_t)ads8688_adc_data_convert(adc_data[6], AI_RANGE);
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adc_real[7] = (uint16_t)ads8688_adc_data_convert(adc_data[7], AI_RANGE);
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}
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void Get_AUTO_RST_Mode_Data(uint8_t chn)
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{
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uint16_t i = 0;
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for(i = 0; i < chn; i++)
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{
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uint8_t data;
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drv_spi_sync_send_rev(kSpiDev_2, data);
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adc_data[i] = data << 8;
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drv_spi_sync_send_rev(kSpiDev_2, data);
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adc_data[i] = data;
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}
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}
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void get_ADS_all(uint8_t chn, uint16_t *adc_real, uint8_t AI_RANGE)
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{
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Get_AUTO_RST_Mode_Data(chn);
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ads8688_get_real_adc_data(adc_real, AI_RANGE);
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}
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void ads8688_init()
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{
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drv_spi_init(kSpiDev_2, kSpiFreq_Div16, kSpiMode_C1E0, SpiFrame_MSBFirst, kGpioType_ADC_Clk, kGpioType_ADC_Miso, kGpioType_ADC_Mosi);
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//drv_spi_set_dma(kSpiDev_2, true, false);
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ads8688_set_autoscan_sequence(0xFF);
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ads8688_set_channel_power_down(0x00);
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ads8688_set_ch_range_select(Channel_0_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_1_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_2_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_3_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_4_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_5_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_6_Input_Range, VREF_U_0_25);
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ads8688_set_ch_range_select(Channel_7_Input_Range, VREF_U_0_25);
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ads8688_enter_auto_rst_mode();
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}
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@ -0,0 +1,95 @@
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#ifndef __ADS8688_H__
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#define __ADS8688_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stdint.h"
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//command register map
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//only care about high 8 bits
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#define NO_OP 0x0000
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#define STDBY 0x8200
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#define PWR_DN 0x8300
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#define RST 0x8500
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#define AUTO_RST 0xA000
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#define MAN_Ch_0 0xC000
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#define MAN_CH_1 0xC400
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#define MAN_Ch_2 0xC800
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#define MAN_Ch_3 0xCC00
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#define MAN_Ch_4 0xD000
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#define MAN_Ch_5 0xD400
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#define MAN_Ch_6 0xD800
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#define MAN_Ch_7 0xDC00
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#define MAN_AUX 0xE000
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//program register map
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//format : 15~9 8 7~0
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// addr W/R DATA
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//register bit15 ~ 9
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#define AUTO_SEQ_EN 0x01
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#define Channel_Power_Down 0x02
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#define Feature_Select 0x03
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#define Channel_0_Input_Range 0x05
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#define Channel_1_Input_Range 0x06
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#define Channel_2_Input_Range 0x07
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#define Channel_3_Input_Range 0x08
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#define Channel_4_Input_Range 0x09
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#define Channel_5_Input_Range 0x0A
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#define Channel_6_Input_Range 0x0B
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#define Channel_7_Input_Range 0x0C
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#define Ch_0_Hysteresis 0x15
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#define Ch_0_High_Threshold_MSB 0x16
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#define Ch_0_High_Threshold_LSB 0x17
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#define Ch_0_Low_Threshold_MSB 0x18
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#define Ch_0_Low_Threshold_LSB 0x19
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#define Ch_7_Hysteresis 0x38
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#define Ch_7_High_Threshold_MSB 0x39
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#define Ch_7_High_Threshold_LSB 0x3A
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#define Ch_7_Low_Threshold_MSB 0x3B
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#define Ch_7_Low_Threshold_LSB 0x3C
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#define Command_Read_Back 0x3F
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//register bit8
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#define WRITE 1
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#define READ 0
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//register AUTO_SEQ_EN bit7 ~ 0
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//default value is FFh(bit7~0 all selected)
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#define CH7_EN 0x80
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#define CH6_EN 0x40
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#define CH5_EN 0x20
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#define CH4_EN 0x10
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#define CH3_EN 0x08
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#define CH2_EN 0x04
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#define CH1_EN 0x02
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#define CH0_EN 0x01
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//register Channel_Power_Down bit7 ~ 0
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//default value is 00h(bit7~0 all powered up)
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#define CH7_PD 0x80
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#define CH6_PD 0x40
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#define CH5_PD 0x20
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#define CH4_PD 0x10
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#define CH3_PD 0x08
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#define CH2_PD 0x04
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#define CH1_PD 0x02
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#define CH0_PD 0x01
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//register Channel_x_Input_Range bit7 ~ 3 is 00000
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//register Channel_x_Input_Range bit2 ~ 0
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#define VREF_B_25 0x00 //channel range:±2.5×VREF = ±10.24V
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#define VREF_B_125 0x01 //channel range:±1.25×VREF = ±5.12V
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#define VREF_B_0625 0x02 //channel range:±0.625×VREF = ±2.56V
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#define VREF_U_0_25 0x05 //channel range:0~2.5×VREF = 0~10.24V
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#define VREF_U_0_125 0x06 //channel range:0~1.25×VREF = 0~5.12V
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#endif /* __ADS8688_H__ */
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